This invention relates to an adder circuit based on a carry look-ahead system.
Adder circuits which are included in computers' central processor units or the like are usually required to operate at high speeds. In adders which are based on a ripple carry system, the propagation of a carry takes considerable time, which is undesirable. Today, adders which are based on a carry look-ahead system are used extensively. A carry select adder, which is shown in FIG. 3.7, page 82 of "Computer Arithmetic: Principles, Architecture, and Design" by K. Hwang (John Wiley & Sons. Inc., 1979) is an example of a prior art carry look-ahead adder. In this adder, a 16-bit input data is divided into four sections each of 4 bits, and two adders are used for each section. Of the two adders, the carry input to one adder is fixed to logic "0" while the carry input to the other is fixed to logic "1". Either one of the sum outputs of the two adders are selected by a multiplexer. The multiplexer is controlled by a carry selector, which has logic elements receiving the output carry from each section adder. In such an adder, the construction of the carry selector is not the same for all the sections, but higher bit sections have more complicated constructions. This presents difficulties in the pattern design when integrating the circuit. Further, where a MOS construction is adopted, a large number of fan-outs of the carry output occur, which reduces speed.